Method and apparatus for checking post-erasure contents of an erasable permanent memory

ABSTRACT

A method of checking post-erasure contents of an erasable permanent memory containing an instruction register and an address register, the method including steps of writing an erasure-checking instruction word into the instruction register, and timing-out for a predetermined duration. The step of writing the instruction word to the instruction register also initiates the steps of opening of the address register, presenting a first address to the address register, iteratively reading the contents of the memory at the address indicated by the address register and incrementing the presented address until the entire memory has been checked, and closing the address register. A device for implementing this method includes a circuit for generating an address-transfer enable signal applied to the address register.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of checking the post-erasurecontents of an erasable permanent memory, especially of EPROM type.

It also concerns a device for its implementation as well as a memoryincorporating this device.

2. Discussion of the Related Art

Rational use of erasable permanent memories, especially of EPROM type,involves systematic checking of the contents of these memories afterevery erasure operation.

Now, hitherto, the checking of the contents of a memory after erasurewas performed by writing an instruction into an instruction register ofthe memory, having the effect of storing the value of an address and ofreading the contents at this address after a necessary recovery timewhich, by way of example, may be of the order of 6 μs.

This operation of writing an instruction and of reading must beperformed for each address to be checked, this entailing significantloss of time in an industrial context. Furthermore, such checking isperformed several times while the memory has not been acknowledged to becompletely erased, which may lead to a total checking time greater thana second.

SUMMARY OF THE INVENTION

An aim of the invention is to remedy these disadvantages by providing amethod of checking the post-erasure contents of an erasable permanentmemory endowed with an instruction register and with an addressregister, comprising a first step of writing an erasure-checkinginstruction word into this instruction register, followed by a secondstep of timing-out of predetermined duration.

According to the invention, the first step of writing the instructionword initiates the following sequence:

opening of the address register,

presentation of a first address,

iterative looping of reading the contents at the address concerned andincrementation of this address until the entire memory has been checked,and

closure of the address register.

Thus, with the method according to the invention, the entire checkingincludes just a single write operation and therefore requires just asingle recovery time-out. With the address register of the memory beingkept open throughout the duration of the checking, the internal addressbus of the memory is then in direct communication with the bus of thedigital system within which the relevant memory is situated and thereading of the memory plane may be performed at a frequency which is notlimited by the recovery time related to the implementation of a writecycle.

According to a preferred form of the invention, the loop comprises astep of reading the memory datum held in the current address, followedby a step of comparison of said datum with a reference erasure datum,said step of comparison leading either to a new iteration in the case ofidentity, or to the execution of a new erasure sequence in the case ofnon-identity.

According to another aspect of the invention, the device for checkingthe post-erasure contents of an erasable permanent memory, especially ofEPROM type, said memory comprising an address register, an instructionregister connected to an internal databus via a status decoder, and anedge detector receiving as input a write enable signal, implementing theabove method, is such that it furthermore comprises means for generatingan address-transfer enable signal applied to the address register on thebasis of a fast erasure-checking signal generated by the instructionregister and of an address clock signal generated by the edge detector.

Moreover, the aforesaid device may be incorporated with EPROM memorieswith various structures.

Other features of the invention will emerge further from the descriptionbelow.

BRIEF DESCRIPTION OF THE DRAWINGS

In the attached drawings given by way of nonlimiting examples:

FIG. 1 is a flow diagram explaining the essential steps of an erasurealgorithm implementing the method according to the invention;

FIG. 2 is a simplified functional diagram of an embodiment of the deviceaccording to the invention;

FIG. 3 is a timing diagram illustrating the sequential running of themethod of checking according to the invention.

FIG. 4 is a block diagram of the EPROM and the digital system thatexecutes the erasure algorithm.

DETAILED DESCRIPTION

The method according to the invention will now be described in detailtogether with the device for its implementation, with reference to FIGS.1 to 4.

The method of checking according to the invention is in practicecontained within an erasure algorithm associated with a specified familyof erasable memories and in particular memories of EPROM type, and thiswill be the case in the remainder of the description. This algorithm Acomprises, generally, and with reference to FIG. 1, an initializingsequence I, an erasure instruction sequence E, an erasure-checkingsequence V which constitutes the method according to the invention,these being followed either by an end sequence F in the case of normalexecution of the algorithm, or by a fault detection sequence D. Thisalgorithm is executed by the outside digital system with which isassociated an EPROM memory 10, with reference to FIG. 4, relating to theerasure procedure, with reference to FIG. 2.

During the initializing sequence I, a programming voltage Vpph of highlevel is applied to an appropriate input Vpp of the memory 10. Theerasure instruction sequence comprises a step E1 of writing an erasurepreparation instruction into an instruction register RC of the memory10. This step causes the setting of internal registers of the memory toerasure mode. It is followed by a step E2 of writing an erasureinstruction into the instruction register RC, succeeded by a step TE oftiming-out of predetermined duration T1, for example of the order of 10ms. It should be noted that the aforesaid sequences and steps correspondto the present state of the art within the field of programmablememories.

On completion of the time-out T1, the outside digital system performs astep V1 of writing an erasure-checking instruction into the instructionregister RC of the memory 10, immediately followed by a step TV oftiming-out of predetermined duration T2, for example of the order of 6μs, required to guarantee the stabilizing of the static circuitries forreading the memory in erasure-checking mode. On completion of thetime-out T2, a specific read and test loop B of the invention isexecuted on all the addresses of the memory 10 concerned. Each iterationof the loop comprises a step VL of reading the datum D present at thecurrent address, a step V2 of comparison of the datum read D with FF_(H)which represents the normal digital contents expected after erasure andwhich therefore constitutes an erasure reference value. If thecomparison is satisfactory, an address test V3 is performed so as tolead either to an incrementation of said address and to an iteration ofthe loop, or, when the entire memory has been inspected, to theend-of-algorithm sequence F during which a low level Vppl is applied tothe programming input Vpp.

If during the comparison step V2 a datum not equal to FF_(H) isdetected, a new erasure sequence E and a new checking sequence V areundertaken iteratively until the erasure-checking is satisfactory. Atest TN on the number N of sequences performed makes it possible tolimit these sequences to a predetermined number, for example equal to3000. Thereafter, the fault indication sequence D for the memory 10 isperformed, during which the programming voltage Vpp is returned to thelow level. It should be noted that the novelty in the invention lies inthe fact that the read and test loop contains neither the sequence forwriting the erasure-checking instruction, nor the time-out of durationT2, this contributing significantly to the reduction in the totalduration of the erasure process.

Elimination of the write cycle and of the time-out previously present inthe checking loop is made possible by an arrangement of the logic forsupervising the programmable memories relating to the method accordingto the invention, as illustrated in the diagram of FIG. 2.

The EPROM-type programmable memory 10 comprises, by way of example andin accordance with the current state of the art, a memory plane PM, atwo-way internal databus 11 connected via an external databus BD to theoutside digital system, a one-way internal address bus 12 connectedthrough an address register RA to an external address bus BA controlledby the outside system. The interconnections of the external digitalsystem 30 and the EPROM 10 are shown in FIG. 4. The EPROM also receivescustomary validation signals CE, OE in accordance with the present stateof the art. These signals are processed by a supervisory logic 21 whosestructure and operation are well known to the expert and therefore willnot be explained here, and which also supervises the use of theprogramming voltage Vpp.

The instruction register RC is connected to the internal databus 11 viaa status decoder R and delivers customary signals required for theinternal instruction of the memory, especially in read, erase orprogramming mode, and also a fast erasure-checking signal FEV specificto the invention. The instruction register RC is controlled by a datumclock signal DCLK itself generated by an edge detector 13 receiving asinput a write enable signal WE, and also delivering a pulse ACLKtriggered by each falling edge of the signal WE.

The address register RA is controlled by a signal ALE (address-transferenable) resulting from a logic NAND operation performed by a logic gate15 between the signal FEV previously inverted by an inverting gate 14and the signal ACLK previously inverted by an inverting gate 22.Transfer of the address actually present on the external address bus BAis enabled over the internal address bus 12 as soon as one or other ofthe signals ACLK and FEV is at the high logic level.

The combination of the decoder R, the detector 13, the logic gates 14,15 and 22, and the address register RA constitutes the erasure-checkingdevice 20 according to the invention, which is normally incorporatedwithin the memory circuit according to the techniques known to theexpert.

The various information transfers performed during execution of theerasure algorithm containing the erasure-checking method according tothe invention will now be described with reference to the timing diagramof FIG. 3.

At the start of the erasure sequence E, the outside digital systemapplies a programming voltage Vpp (for example 12 volts) and generates alow pulse on the write enable input WE which, when quiescent, is at thehigh logic level, then delivers onto the data bus BD aprepare-for-erasure instruction word PE which is taken into account bythe instruction register after decoding the signal WE. Next, the outsidesystem again generates a low pulse on the write enable input WE, thensends an erasure instruction word CE via the databus BD. 0n completionof this sending, a time-out TE is performed so as to guarantee correcterasure of the entire memory plane. Next, the outside system againgenerates a low pulse on the write enable input WE, then anerasure-checking instruction word CV via the databus. Thiserasure-checking instruction word CV is decoded on completion of a pulseWE and leads to the generation of the signal FEV (cf. FIG. 2). Thetime-out of duration T2, for example 6 μs, is activated so as toguarantee the stabilizing of the static circuitries for reading inerasure-checking mode. Placing FEV at the high logic level causes thesignal ALE to pass to the high level and therefore the register RA toopen, thus becoming transparent. The outside system can then generateread cycles by applying the successive addresses A0, A1, A2, . . . AN onthe address bus BA, and by receiving back, on the databus BD, therespective data D0, D1, D2, . . . DN for checking. The comparisons ofthe data read with reference data (normal digital contents expectedafter erasure) are naturally performed in the outside digital system ashas been indicated. It is readily observed that, with the methodaccording to the invention, the inspection of the memory plane is nolonger hindered by a systematic writing of an erasure-checkinginstruction word which would contribute to slowing down the erasureprocess significantly.

The method of checking according to the invention is particularlyappropriate to the FLASH EPROM memories for which it was initiallydevised.

Of course, the invention is not limited to the examples which have justbeen described and numerous other contrivances of the invention may beenvisaged without departing from the scope of the present invention.

Thus, the application of the method according to the invention is notlimited to a particular type of EPROM memory, but may be envisaged forany type of programmable and erasable memory.

Moreover, the opening of the address register may be effected by logicarrangements other than that described hereinabove merely by way ofexample, depending on the logic resources actually available within thetopography of the memory circuit.

What is claimed is:
 1. A method of checking post-erasure contents of anerasable permanent memory, the memory being especially of EPROM type andcomprising an instruction register and an address register, the methodbeing executed as part of an erasure sequence and comprising the stepsof:writing an erasure-checking instruction word into said instructionregister once during the erasure sequence, wherein the step of writingthe erasure-checking instruction word once initiates a timing-out for apredetermined duration and the following checking sequence, occurringafter said timing-out; opening of the address register; presentation ofa first address to the address register; iteratively reading and testingthe contents of the permanent memory at the presented address; and oneof incrementing the address until the entire memory has been checked andexecuting a new erasure sequence; and one of closing of the addressregister when the entire memory has been checked and exiting the erasuresequence when a predetermined number of erasure sequences has beenperformed.
 2. The method as claimed in claim 1, wherein the reading andtesting step comprises the steps of:reading a memory datum held in thepresented address of the memory; comparing said memory datum with areference erasure datum; performing a new reading and testing iterationwhen the memory datum is identical to the reference datum; and otherwiseexecuting said new erasure sequence step when the datum is not identicalto the reference datum.
 3. The method as claimed in claim 2, wherein thereading and testing step further comprises a step of testing thepresented address to determine if the entire memory has been checked. 4.The method as claimed in claim 2, wherein the step of executing a newerasure sequence includes a step of comparing a number of sequenceswhich have been performed with a threshold value, and if the number ofsequences exceeds the threshold value a fault indication is given.
 5. Asystem for checking post-erasure contents of an erasable permanentmemory, said system comprising;a memory, especially of EPROM type, saidmemory comprising an address register, an instruction register connectedto an internal data bus via a status decoder, and an edge detectorreceiving as an input a write enable signal; means for writing anerasure-checking instruction word into said instruction register andtiming-out for a predetermined duration, once during an erasuresequence; means for presenting an address to the address register; meansfor iteratively reading and testing contents of the memory at theaddress presented and for incrementing the address presented until theentire memory has been checked or a new erasure sequence is executed;means for executing a new erasure sequence when the datum in the memoryat the address presented does not match a reference datum for thataddress; and means, in said memory, for generating an address-transferenable signal and for outputting the address-transfer enable signal tothe address register.
 6. The device as claimed in claim 5, wherein themeans for generating the address-transfer enable signal comprise atwo-input NAND logic gate receiving as inputs a logic inverse of anaddress clock signal generated by the edge detector and a logic inverseof a fast erasure-checking signal generated by the instruction register.7. A system for checking post-erasure contents of an erasable permanentmemory, the system comprising:a memory, especially of an EPROM type,said memory comprising an address register, an instruction registerconnected to a first internal databus via a status decoder, and an edgedetector which receives as an input a write enable signal; a two wayexternal databus coupled to the first internal databus which transmitsan erasure-checking instruction, from a digital system external to saidmemory, to the first internal databus, once during a single erasuresequence; a logic circuit for generating address-transfer enable signalto said address register which enables said address register to transferan address present on a one way external address bus to a memory planeof the memory, the logic circuit having an input coupled to an output ofthe instruction register and a second input coupled to an output of theedge detector, and having an output coupled to an input of the addressregister; a second internal databus having an input coupled to an outputof the address register and an output coupled to an input of the memoryplane, the memory plane also having an output coupled to the firstinternal databus, wherein said second internal databus carries theaddress present on the one way external databus to the memory plane, andthe datum at that address is sent along said two way external databus tosaid digital system for checking.
 8. A device as claimed in claim 7,wherein the logic circuit comprises:an inverter having an input coupledto the output of the instruction register and an output; a secondinverter having an input coupled to the output of the edge detector andan output; a logic gate having a first input coupled to the output ofthe first inverter and a second input coupled to the output of thesecond inverter and an output coupled to the input of the addressregister.